1. Field of the Invention
The present invention relates to a bus control system between a microprocessor and peripheral LSIS thereof, and more particularly to a bus control system which can transfer a command and data between chips more efficiently using the bus. The present invention also relates to a bus control system which allows a burst transfer of data more efficiently.
2. Description of the Related Art
A microprocessor is connected with peripheral chip sets and is mounted on a board of a computer. For example, a microprocessor is connected to a PCI bus where a peripheral device is connected via a bridge IC, and the microprocessor and the bridge IC are connected via a bus.
In other words, the microprocessor issues a command and data, and sends them to the bridge IC via the bus. From the bridge IC as well, a command and data from the device connected with the bridge IC are sent to the microprocessor via the bus. Commands typically include a read and a write, and an address is added to a read command, and an address and data are added to the write command. Data includes data which was read responding to a read command, and write data which corresponds to a write command.
In another example, a microprocessor is connected to a memory controller IC via a bus, and reads from or writes to a memory or another processing LSI connected to the memory controller. The microprocessor is also read or written by the processing LSI.
FIG. 1 are diagrams depicting a conventional bus control between a microprocessor and a peripheral LSI. FIG. 1A is a connection diagram between a microprocessor A and a bridge chip B, and a command (including address and read/write) issued by the microprocessor A is sent to the bridge chip B via a command bus 10. The bridge chip B is connected to a bus 100 which is connected to, for example, an I/O device or a memory controller.
When a command is issued from the microprocessor A to the chip B in the configuration shown in FIG. 1A, it is assumed that the chip B side has the capability to simultaneously process a maximum of four commands from the microprocessor A. In other words, the number of stages of the command buffer for reception in the chip B is four, where a maximum of four commands can be simultaneously received and held.
When the microprocessor A continuously issues commands to the chip B, the chip B cannot process the fifth command. Therefore, the chip B must notify the microprocessor A that the chip B cannot accept the fifth command. In prior art, when the chip B is processing four commands internally and cannot receive a new command, the chip B outputs the busy signal BUSY to the microprocessor A to stop the microprocessor A from issuing a new command.
The strobe signal STRB shown in the time chart in FIG. 1B is a strobe signal to indicate that the command (e.g. address, READ/WRITE) on the command bus 10 is in a valid cycle. Each time the microprocessor A sends a command, the microprocessor A outputs the strobe signal STRB to indicate that the command is valid. In FIG. 1B, four commands, 1-4, are continuously issued from the microprocessor A to the chip B in the cycles 1 to 4, but the internal command buffer of the chip B becomes full when the fourth command 4 is received. So the chip B outputs the busy signal BUSY to the microprocessor A from the next cycle 5. The microprocessor A issues the fifth command in the cycle 5, but recognizes that the chip B does not receive the command 5 by the busy signal BUSY.
In this prior art, the chip B outputs the busy signal BUSY from the cycle next to the cycle when the command buffer for reception became full. This method is possible in an area where the operating frequency is slow, but if the operating frequency is high, the busy signal BUSY cannot be output at the cycle next to the cycle when the command buffer becomes full. Therefore, the microprocessor A, when issuing the command, must confirm whether the busy signal BUSY was output from the chip B before issuing the next command, so that in the end the microprocessor A can issue the next command only one cycle after issuing a command.
As the time chart in FIG. 1B shows, if the output of the busy signal BUSY delays one cycle, the busy signal BUSY is output from the cycle 6, so the microprocessor A erroneously recognizes that the fifth command 5, which was output in the cycle 5, was received by the chip B. To prevent this, the microprocessor A issues the next command two cycles after issuing the command, and checks whether the command was received by the presence of the busy signal BUSY at that time, as shown in the time chart in FIG. 1C. Therefore the microprocessor A can issue a command only once every two cycles, which decreases the bus access efficiency.
The above problem occurs not only to a command bus but to a data bus as well. Also, the same problem occurs not only when a command or data is transferred from the microprocessor A to the chip B, but also when a command or data is transferred in the opposite direction.
Also when a command or data is transferred between chips via a two-way bus, a bus arbiter circuit is required to decide which chip has the bus access right. But the above conventional system is inappropriate to employ a two-way bus, and the number of buses are required to be doubles.